This invention relates to a semiconductor device equipped with a plurality of semiconductor elements of a MOS structure, and to a method for manufacturing the semiconductor device.
In accordance with recent development of semiconductor techniques, in particular, of shrinkage techniques, shrinkage of memory cells, i.e. high integration of a semiconductor device, has been rapidly advanced. As a result, problems have occurred concerning variance in shape (area) between memory cells due to variance in processing or misalignments in lithography.
In particular, in the case of a non-volatile semiconductor memory device such as an EEPROM (Electrically, Erasable Programmable Read Only Memory) having cells of a double gate structure (floating gate/control gate structure), memory cells have variance in coupling ratio C2/(C1+C2) between the electrostatic capacitance Cl of a gate dielectric film interposed between a semiconductor substrate and a floating gate electrode, and the electrostatic capacitance C2 of a dielectric film interposed between the floating gate electrode and a control gate electrode (hereinafter referred to as an "interelectrode dielectric film").
The inventor of this invention previously filed an application directed to an invention capable of effectively reducing the variance in coupling ratio due to lithography or other treatments (Japanese Patent Application No. 7-54791). However, there is not realized effective reduction of the variance in coupling ratio due to those variance in shape among cells (in shape among floating gate electrodes or among control gate electrodes), which is caused since crystal grains contained in a polysilicon film forming the floating gate electrode or the gate electrode are not controlled in number, shape, volume, direction of plane, etc.
FIG. 1A is a schematic sectional view of memory cells incorporated in an EEPROM, showing variance in crystal grain between floating gate electrodes, and variance in shape (gate width) therebetween. For simplifying the figure, a dielectric film (oxide film) incorporated in the EEPROM is not hatched. FIG. 1B is a plan view, taken along lines 1B--1B of FIG. 1A. Further, FIG. 1C is an enlarged view of a 1C portion shown in FIG. 1B.
In FIGS. 1A-1C, reference numeral 1 denotes a p-type silicon substrate, reference numeral 2 an n-type source-drain diffusion layer, reference numeral 3 a tunnel gate oxide film, reference numeral 4 a floating gate electrode, reference numeral 5 an interelectrode dielectric film formed between gate electrodes, reference numeral 6 a control gate electrode, reference numeral 7 a dielectric film for isolation, and reference numeral 11 an interlayer dielectric film. The floating gate electrode 4 and the control gate electrode 6 are formed of polysilicon films. The interelectrode dielectric film 5 consists of an oxide film, a nitride film and another oxide film. Reference numeral 12 denotes the nitride film included in the interelectrode dielectric film 5.
Variance in the number of crystal grains will occur partially because crystal grains in the floating gate electrode 4 are grown during a heat treatment performed after forming of the electrode, and accordingly the number of the grains is varied and protrusions 8 are formed. Another reason for occurrence of such variance is that grain boundaries are oxidized during an oxidation treatment performed after the forming of the electrode, and accordingly retractions 9 are formed. Moreover, grain growth is enhanced by the oxidation process. Yet another reason is that the oxidation speed differs between crystal grains depending upon their orientation, and accordingly the number of the grains is varied and steps 10 are formed.
The above-described variance in the number of crystal grains or in shape (gate width) between semiconductor elements due to the heat treatment, the thermal oxidation treatment or variance in oxidation speed will increase the variance in coupling ratio. Moreover, an oxide film formed directly under the grain boundary has high conductivity (see "Technical Digest of International Electron Devices Meeting 1994, p847), and hence its dielectric characteristics are liable to degrade. Accordingly, where those grain boundaries of the floating gate electrodes 4 which contact the tunnel gate oxide film 3 have different lengths, the amount of current for writing or erasing is liable to vary.
As described above, in the conventional EEPROMs, the number of crystal grains contained in a polysilicon film, which constitutes the floating gate electrode or the control gate electrode, is not controlled. Thus, in the conventional EEPROMs, there is not reduced the range of variance in coupling ratio due to variance in the number of crystal grains between floating gate electrodes or between control gate electrodes.